1. Field of the Invention
The present invention pertains to the formation and planarization of polymeric dielectric films on semiconductor substrates, and more particularly to a process for achieving high chemical mechanical polish removal rates when planarizing these films.
2. Description of the Prior Art
A continuing trend in semiconductor technology is the formation of integrated circuit (IC) chips having more and faster circuits thereon. Such ultralarge scale integration has resulted in a continued shrinkage of feature sizes with the result that a large number of devices are made available on a single chip. With a limited chip surface area, the interconnect density typically expands above the substrate in a multi-level arrangement and the devices have to be interconnected across these multiple levels. The interconnects must be electrically insulated from each other except where they are designed to make contact. Usually electrical insulation requires depositing or spinning dielectric films onto a surface. It is known in the art that organic polymer dielectric films have important applications in advanced integrated circuit multilayer interconnect fabrication. This is due to their superior electrical insulating characteristics compared to the standard integrated circuit interconnect insulator, silicon dioxide. It is well known that faster signal processing, lower power consumption, and reduced noise in circuitry results by the replacement of silicon dioxide by selected organic polymers, in particular those which have relatively low dielectric constants, such as those with dielectric constant values below 3.
Integrated circuits are typically fabricated as identical, adjacent units on a silicon wafer substrate. Fabrication involves sequential deposition and patterning of a large number of individual thin films comprised of a variety of conductors, insulators, and processing chemicals. A key processing difficulty associated with the formation of local interconnects is the topography of the device surface. Not only is the substrate surface itself quite non-planar, but device forming processes additionally create topographical irregularities. Loss of planarity can cause many problems which can adversely impact manufacturing yield including failure to open vias due to interlevel dielectric thickness disparity, poor adhesion to underlying materials, step coverage, as well as depth-of-focus problems. As optical lithography techniques are used to define smaller and smaller features, the depth of focus of the exposure tool decreases. In order to effectively fabricate multiple layers of interconnects it has become necessary to globally planarize the surface of certain layers during the multi-step process. Planarizing smoothes or levels the topography of microelectronic device layers in order to properly pattern the increasingly complex integrated circuits. IC features produced using photolithographic techniques require regional and global dielectric planarization where the lithographic depth of focus is extremely limited, i.e., at 0.35 .mu.m and below. As used herein, the term "local planarization" refers to a condition wherein the film is planar or flat over a distance of 0 to about 5 linear micrometers. "Regional planarization" refers to a condition wherein the film is planar or flat over a distance of about 5 to about 50 linear micrometers. "Global planarization" refers to a condition wherein the film is planar or flat over a distance of about 50 to about 1000 linear micrometers. Without sufficient regional and global planarization, the lack of depth of focus will manifest itself as a limited lithographic processing window. Chemical mechanical polishing (CMP) has been effectively used in the art to essentially planarize the entire surface of such a layer. CMP has a unique advantage in that it can rapidly remove elevated topographical features without significantly thinning flat areas.
An important characteristic of a useful CMP process is a high removal rate of the films. Removal rates of nominally 2000 .ANG./minute to 4000 .ANG./min are currently considered to be relatively high, and rates below 1000 .ANG./min are generally considered to be relatively low. Assuming that other performance characteristics are not compromised, CMP removal rates of nominally 2000 .ANG./min to 4000 .ANG./min are desirable and acceptable in IC fabrication processes. Prior art methods for increasing the CMP removal rates include increasing the down force associated with the polishing pad impinging on the film being polished during the CMP process; increasing the size and/or concentration of particles contained in the polishing slurry used during the CMP process; modifying the chemical composition of the slurry solution, for example by changing the pH, addition of surfactants or dispersants; and utilizing a CMP polishing pad constructed of a relatively harder material.
With the introduction of organic polymer dielectrics in place of silicon dioxide as the IC interconnect insulator, a need exists for methods to conduct efficient CMP of polymer films. Unfortunately, organic polymer films typically exhibit low CMP removal rates when fully cured and subsequently polished with slurries designed for SiO.sub.2 based dielectrics. Under a variety of experimental conditions, quite low values (for example, less than 1000 .ANG./min) are observed for dielectric films prepared from such polymer chemical compositions as polyarylene ethers and fluorinated polyarylene ethers. Examples of other organic polymer dielectrics and articles produced therefrom are disclosed in U.S. Pat. Nos. 5,145,936; 5,108,840; 5,115,082;5,114,780; 5,155,175; 5,179,188; 5,250,667; 5,235,044; 5,173,542; and 5,270,453. In all these cases, prior to carrying out the CMP process, the films were deposited from a lacquer by spin-coating on to the silicon substrate, and then subjected to a full thermal cure.
Polymeric films which are deposited in thin film form using lacquers and spin-coating techniques have a distinctive characteristic when compared to polymeric films which are deposited by physical or chemical deposition techniques (PVD or CVD respectively). In the case of the spin-on films, they invariably require curing to harden and set the film. It would be desirable to provide an improved process whereby polymeric films of the type mentioned could be subjected to a CMP planarization treatment a high film removal rate.
The present invention provides a method for achieving a high CMP removal rate with organic polymer dielectrics using CMP techniques and conditions. It has been found that when polymeric dielectric thin films are deposited by spin coating, the CMP polish rates are a function of the extent of cure of the films. According to the process of the invention, the deposited films are partially cured, subjected to CMP and then subjected to a final cure. It has been found that if the deposited polymer films are only partially cured, their CMP removal rates are much higher, on the order of about 2000 .ANG./min or higher, when compared to the removal rates for similar films which are more fully cured prior to CMP. For these latter, fully cured films, CMP removal rates under standard conditions are typically less than about 1000 .ANG./min. The present invention also provides a method for tailoring the CMP removal rate for dielectric polymers by first forming a calibration curve composed of data plotting the CMP removal rate as a function of the degree of cure, and tailoring the CMP removal rate to determine a desired value over the accessible removal rate range.